1. Field of the Invention
The present invention relates to methods and structures used to perform precision alignment of substrates, for example, semiconductor wafers.
2. Description of the Related Art
Wafer-level assembly techniques, i.e., joining and fabricating elements of chip packages at the wafer-level, can offer certain efficiencies, in that the amount of processing can potentially be reduced. A semiconductor wafer can contain hundreds of individual chips. Therefore, doing fabrication steps at the wafer-level can reduce the total amount of processing needed to make chip packages from all the chips of the wafer.
Wafer-level assembly techniques can be used to form electrically connected stacked wafer assemblies which can then be severed into individual assemblies each containing a plurality of stacked chips. Each assembly can be further processed into a package. However, wafer-level processing requires very accurate and precise alignment processes.
Further improvements in techniques used to align one wafer to another, such as for wafer-level assembly processes, are desirable.